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Digital Delay Generator DG645 ... from $4195
DG645 ultra-low jitter delay generator
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DG645 Digital Delay Generator
  • 4 pulse outputs
  • 8 delay outputs (opt.)
  • <25 ps rms jitter
  • Trigger rates to 10 MHz
  • Precision rate generator
  • Fast transition times
  • Ovenized or Rb timebase (opt.)
  • Ethernet, GPIB and RS-232
The DG645 is a versatile digital delay/pulse generator that provides precisely defined pulses at repetition rates up to 10 MHz. The instrument offers several improvements over older designs — lower jitter, higher accuracy, faster trigger rates, and more outputs. The DG645 also has Ethernet, GPIB and RS-232 interfaces for computer or network control of the instrument.
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DG645 Digital Delay/Pulse Generator

The DG645 is a versatile digital delay/pulse generator that provides precisely defined pulses at repetition rates up to 10 MHz. The instrument offers several improvements over older designs — lower jitter, higher accuracy, faster trigger rates, and more outputs. The DG645 also has Ethernet, GPIB and RS-232 interfaces for computer or network control of the instrument.

Delay Generator Timing

All digital delay generators measure time intervals by counting cycles of a fast clock (typically 100 MHz). Most digital delay generators also have short programmable analog delays to achieve time intervals with finer resolution than the clock period. Unfortunately, one clock cycle of timing indeterminacy (typically 10 ns) can occur if the trigger is not in phase with the clock.

The DG645 eliminates timing indeterminacy by measuring the timing of triggers with respect to the internal clock and compensating the analog delays. This approach reduces the jitter by about 100× and allows the internal rate generator to operate at any rate — not just a sub-multiple of the clock frequency.

Triggering

The DG645 has many trigger modes. An internal rate generator, with less than 100 ps period jitter, may be set from 100 µHz to 10 MHz with 1 µHz resolution. An external trigger input, with adjustable threshold and slope, can trigger a timing cycle, a burst of cycles, or a single shot. A single shot can be triggered with a key press. A line trigger operates synchronously with the AC mains. A rear-panel trigger inhibit input can disable the trigger or any of the pulse outputs during a timing cycle.

The DG645 supports a number of complex triggering requirements via a trigger holdoff and prescaling feature.

Trigger holdoff sets the minimum time between successive triggers. This is useful if a trigger event in your application generates a significant noise transient that needs time to decay away before the next trigger is generated. Trigger holdoff can also be used to trigger the DG645 at a sub-multiple of the input trigger rate.

Trigger prescaling enables the DG645 to be triggered synchronously with a much faster source, but at a sub-multiple of the original trigger frequency. For example, the DG645 can be triggered at 1 kHz, but synchronously with a mode locked laser running at 80 MHz, by prescaling the trigger input by 80,000. Furthermore, the DG645 also contains a separate prescaler for each front-panel output, enabling each output to operate at a sub-multiple of the trigger rate.

Front-Panel Outputs

There are five front-panel outputs: T0, AB, CD, EF and GH. The T0 output is asserted for the duration of the timing cycle. The leading edge of T0 is the zero time reference. The programmed delays (A, B, C, D, E, F, G and H) are set from 0 s to 2000 s, with 5 ps resolution, to control the timing of the leading and trailing edges of the four pulse outputs.

Each front-panel output can drive a 50 Ω load and has a 50 Ω source impedance. Output amplitudes can be set from 0.5 to 5.0 V, and output offsets can range over ±2 VDC to source virtually any logic level (NIM, ECL, PECL, CMOS, etc.). Output transition times are less than 2 ns at any output amplitude.

Rear-Panel Outputs

Optional rear-panel outputs are available to support diverse applications. Option 1 provides a T0 output and eight programmed delays (A, B, C, D, E, F, G and H) at 5 V logic levels, with transition times less than 1 ns. Option 2 provides these same outputs but as 30 V, 100 ns pulses with less than 5 ns transition times for timing distribution in high noise environments. Option 3 provides eight combinatorial outputs which deliver one to four pulses at 5 V logic levels with less than 1 ns transition times. Each output has a 50 Ω source impedance.

Timebases

The standard time base has an accuracy of 5 ppm, and a jitter of 10-8, which is suitable for many applications. Optional timebases are available for users who require better rate and delay accuracy or reduced rate and delay jitter.


Timing error vs. delay


The timing error for a 1 s delay can be as large as 5 µs for the standard timebase, 200 ns for the OCXO timebase, but is only 500 ps for the rubidium timebase (all 1 year after calibration.) See Timing Error vs. Delay graph to right

For short delays the jitter is typically 20 ps. However, for a 1 s delay, the standard timebase can contribute up to 10 ns of jitter, while the optional timebases contribute less than 10 ps of additional jitter. See Jitter vs. Delay graph to right

 

Fast Rise Time Module

The DG645 front-panel outputs have transition times of less than 2 ns. The SRD1 is an accessory, built into an in-line BNC connector, which reduces the rise time of a front-panel output to less than 100 ps. Up to 5 SRD1s can be attached to the front panel to reduce the rise time of all of the outputs.


 

 

 

 

 

 

Phone: (408)744-9040 • Fax: (408)744-9049 • email: info@thinkSRS.comwww.thinkSRS.com

DG645 Digital Delay/Pulse Generator

Delays

Channels 4 independent pulses controlled in position and width. 8 delay channels available as an option (see Output Options below)
Range 0 to 2000 seconds
Resolution 5 ps
Accuracy 1 ns + (timebase error × delay)
Jitter (rms)
     Ext. trig. to any output
     T0 to any output

25 ps + (timebase jitter × delay)
15 ps + (timebase jitter × delay)
Trigger delay 85 ns (ext. trigger to T0 output)

External Trigger

Rate DC to 1/(100 ns + longest delay). Maximum of 10 MHz
Threshold ±3.50 VDC
Slope Trigger on rising or falling edge
Impedance 1 MΩ + 15 pF

Internal Rate Generator

Trigger modes Continuous, line or single shot
Rate 100 µHz to 10 MHz
Resolution 1 µHz
Accuracy Same as timebase
Jitter (rms) <25 ps (10 MHz/N trigger rate)
<100 ps (other trigger rates)

Burst Generator

Trigger to first T0
     Range
     Resolution

0 to 2000 s
5 ps
Period between pulses
     Range
     Resolution

100 ns to 42.9 s
10 ns
Delay cycles per burst 1 to 232 - 1

Outputs (T0, AB, CD, EF and GH)

Source impedance 50 Ω
Transition time <2 ns
Overshoot <100 mV + 10 % of pulse amplitude
Offset ±2 V
Amplitude 0.5 to 5.0 V (level + offset <6.0 V)
Accuracy 100 mV + 5 % of pulse amplitude

General

Computer interfaces GPIB (IEEE-488.2), RS-232 and Ethernet. All instrument functions can be controlled through the interfaces.
Non-volatile memory Nine sets of instrument configurations can be stored and recalled.
Power <100 W, 90 to 264 VAC, 47 Hz to 63 Hz
Dimensions 8.5" × 3.5" × 13" (WHL)
Weight 9 lbs.
Warranty One year parts and labor on defects in materials & workmanship
   
Output Options

Option 1 (8 Delay Outputs on Rear Panel)

Outputs (BNC) T0, A, B, C, D, E, F, G and H
Source impedance 50 Ω
Transition time <1 ns
Overshoot <100 mV
Level +5 V CMOS logic
Pulse characteristics
     Rising edge
     Falling edge

At programmed delay
25 ns after longest delay

Option 2 (8 High-Voltage Delay Outputs on Rear Panel)

Outputs (BNC) T0, A, B, C, D, E, F, G and H
Source impedance 50 Ω
Transition time <5 ns
Levels 0 to 30 V into high impedance, 0 to 15 V into 50 Ω (amplitude decreases by 1 %/kHz)
Pulse characteristics
     Rising edge
     Falling edge

At programmed delay
100 ns after the rising edge

Option 3 (Combinatorial Outputs on Rear Panel)

Outputs (BNC) T0, AB, CD, EF, GH, (AB+CD), (EF+GH), (AB+CD+EF), (AB+CD+EF+GH)
Source impedance 50 Ω
Transition time <1 ns
Overshoot <100 mV + 10 % of pulse amplitude
Pulse characteristics
     T0, AB, CD, EF, GH
     (AB+CD), (EF+GH)
     (AB+CD+EF)
     (AB+CD+EF+GH)

Logic high for time between delays
Two pulses created by the logic OR of the given channels
Three pulses created by the logic OR of the given channels
Four pulses created by the logic OR of the given channels

Option SRD1 (Fast Rise Time Module)

Rise time <100 ps
Fall time <3 ns
Offset -0.8 V to -1.1 V
Amplitude 0.5 V to 5.0 V
Load 50 Ω
 
 
 
 
 
Phone: (408)744-9040 • Fax: (408)744-9049 • email: info@thinkSRS.com • www.thinkSRS.com